Interconnect Solutions

• Integration of cantilever springs in Al and Cu metal redistribution layers for advanced packaging technology for use in high thermal stress environments.

• Cu/Sn pillar bonding using custom epoxy formulation for thermal compression bonding.

• 3D chip stacking and extreme thinning of SOI wafers.

• Low profile (~10 µm) die thickness and formation of inter-wafer through vias

Privatran staff are working on small-pitch indium flip-chip and high-thermal-stress microconnect systems for hybridized, low-temperature Infrared focal plane arrays.

Microconnect stress, strain and electrical modeling and simulation have identified several potential commercially-viable approaches, and PrivaTran is seeking funding to further develop this technology.

PrivaTran employees have key experience in metal and polyimide microconnect materials selection, implementation of materials for small-pitch bump-bonded microconnects, high-precision pick-and-place alignment, and low-temperature thermal compression bonding, all of which are required to design and build a successful microconnect system to repeatedly withstand thermal cycling down to 77ºK.

Whether your interface requires wire-bonding or advanced small-pitch bump bonding, the PrivaTran team can design and develop the interconnect that you need. Working with key partners in the packaging industry such as TLMI Inc. (http://www.tlmicorp.com), with process and development capability for both redistribution layers and wafer-scale bump interconnect, PrivaTran can provide multi-chip modules custom-suited to your needs.

The TLMI partnership provides materials deposition expertise including electro-plating, sputtering and spin-coating, and expertise in chip re-distribution layer (RDL) design and fabrication, photolithography, wafer cleaning, back grinding, dicing, and wafer-scale bumping.

The design expertise of the PrivaTran staff ranges from sensor-level to transistor-level to the packaging and systems level so that the PrivaTran team provides the complete solution for sensor interconnect to leading-edge microelectronics.

Privatran staff and partners have extensive experience in:

Microfabrication and process development for optical waveguide devices and wafer-bump processing for flip-chip applications
LED packaging
Process and device development for both wafer-bumping and polymer Thermo-Optic Integrated Circuit (TOIC) product lines
Materials deposition expertise includes electro-plating, sputtering and spin-coating
Expertise in mask layout services, chip re-distribution layer (RDL) design
and fabrication, photolithography, wafer cleaning, back grinding, dicing, and wafer-scale bumping

Silicide formation on silicon, Cu metal interconnects and advanced packaging